Category: FPGA

Carlitos 1, Xilinx 0

Xilinx Spartan
Xilinx Spartan

I spent countless hours trying to install the free version of the Xilinx software on may windoze Virtual machine and I have finally succeed.

I must say that although I have never used Xilinx ISE Webpack, store I already hate it. It come in a huge installation archive (2.7 GB) and an equally huge update archive (2.4 GB). The option to use the “slim” installer (88 MB) is worthless since there is no ways of saving the required files for an eventual reinstallation (which was needed twice in my case).

Anyway, here after installing/uninstalling/installing many times I finally got it to work. And this very lengthy and painful process reminded me why the Open Source world is so much more convenient. Installing a full linux distribution with tons of extra programs takes half the required storage and a third of the time. Too bad FPGA programming tools are ruled by the chip manufacturers.

All this painful process was required in order to get my new NanoBoard 3000 running. Hopefully I wont have to use Xilinx ISE anytime soon. Altium Designer was much easier to install and requires less storage.

I am the luckiest Engineer ever

A few weeks ago, I received a very pleasant message: Altium, an FPGA development board manufacturer and IDE developer, contacted me asking If I wanted to try the (excessively cool) brand new development board (the NanoBoard 3000) for free.  Of course, I immediately (and quite emphatically) said YES.

The Altium NanoBoard 3000
The Altium NanoBoard 3000

Now that I got it, I’m dying to have some spear time in order to try out their awesome board with their quite intriguing IDE.

About the Hardware

The NanoBoard 3000 is a beautiful piece of equipment. It boasts lots of cool peripherals and is built and packed as a luxury electronics product. It is a very good looking piece of equipment while remaining perfectly functional, it beats by far all the other development boards I am familiar with (i.e. the Altera DE2 board and the Lattice Mico32 development board) while remaining much cheaper (around 50% of their price).

NanoBoard 3000 Unboxing
NanoBoard 3000 Unboxing

Features

Here is a selection of the NanoBoard’s features from Altium’s Wiki I find most prominent:

  • A Xilinx Spartan-3AN device (XC3S1400AN-4FGG676C)

    Nanoboard 3000 Front
    Nanoboard 3000 Front
  • 4 Serial SPI Flash memory devices
  • Programmable clock 6 to 200 MHz, accessible by Altium Designer or by an FPGA design
  • SPI Real-Time Clock with 3V battery backup
  • Adjustable voltage regulators set to generate 1.2V, 1.8V, 2.5V and 3.3V power
  • 256K x 32-bit common-bus SRAM (1MB)
  • 16M x 32-bit common-bus SDRAM (64MB)
  • 8M x 16-bit common-bus 3.0V Page Mode Flash memory (16MB)
  • Dual 256K x 16-bit independent SRAM (512KB each)
  • 256K x 16-bit independent SRAM (512KB)
  • 8 RGB LEDS
  • 5 generic push-button switches
  • 4-channel 8-bit ADC, SPI-compatible
  • 4-channel 8-bit DAC, SPI-compatible
  • 4x isolated IM Relay channels
  • 4x PWM power drivers
  • Screw terminal headers for ADC/DAC/Relay/PWM interfaces
  • SD (Secure Digital) card readers:
    • One for use by the Host Controller FPGA
    • One for use by the User FPGA
  • SVGA interface (24-bit, 80MHz)

    NanoBoard 3000 Back
    NanoBoard 3000 Back
  • 10/100 Fast Ethernet interface
  • USB 2.0 High-Speed interface
  • RS-232 Serial Port – DB9M
  • RS-485 Serial Port – ‘RJ45’
  • 240 x 320 TFT LCD with touch screen
  • 8-way DIP-switch
  • Stereo 2W audio power amplifier with 3.5mm test input jack and DC volume control
  • 24-bit Stereo Audio CODEC with I2S-compatible interface
  • Stereo audio jacks (3.5mm):
    • Line In / Line Out
    • Headphones
  • Speakers on a separate (attached) board
  • MIDI interface
  • Diagnostics interface – PCI Express (PCIe) edge connector for connection of automated test equipment (ATE)
  • 1.8″ ATA/IDE connector providing access to user LED and generic switch I/O
  • Remote Control and IR interface.

I should post some further details and perhaps even a simple test project soon (as soon as I get Altium Designer and Xilinx ISE installed and running)

Speech Recognition Using FPGA Technology

My friends David and Kanwen, and I implemented a speech recognition system on an FPGA development board (Altera DE2 Board) for the Design Project course at McGill (ECSE 494). We did this in two step: first we wrote a prototype for the algorithm in MATLAB (I’ll maybe port it to Octave), and then we did the hardware description for the FPGA.

MATLAB Prototype

Inspired by the algorithm described in a site from the University of Toronto, we wrote two MATLAB scripts: train.m and recogniz.m.

train.m deals with the training phase, in which many versions of a sound (a spoken word for instance) are input and averaged in the frequency domain thus generating the sound’s “reference fingerprint”.

recogniz.m deals with the recognition phase, where a sound is input, translated to the frequency domain (i.e. Its fingerprint is generated), and compared to the reference fingerprint by computing the euclidean distance between them (as if both fingerprints where vectors).

Both scripts need to detect the beginning of the sound (i.e tell when the spoken word begins). They do so by averaging two adjacent 1024-sound-samples groups (in the time domains) and computing the difference between the averages. So, if there is a sudden increase in the sound’s amplitude, the difference will be significant and the sound is assumed to start after that sudden increase. The sound’s length is fixed to 1,024 s (see the picture below for more details)

Note that the scripts use 16-bit WAV files as input @ 22050 Hz (this is the default windows sound recorder output, since I could not do it in Linux because the mic did not wanted to work). The sound input is downsampled and quantized in order to get it down to 8 bit /sample @ 5 kHz for processing.

Also you might encounter problems if the sound file is too short (it should last for more than 1,1 s), or if its volume level is too low (this happens because the detector threshold is fixed).

Hardware Implementation

Once we had played enough with the MATLAB prototype parameters, we mapped the algorithm into combinational logic and finite state machines (FSM) by breaking it down into independent modules.

For more details about the hardware implementation and the project in general you can read the full project report. You may also want to see the slides for a presentation we did (below).

Unfortunately, I cannot post the project files (i.e. VHDL code).

Here is a little video demo, enjoy:

Note that all the documentation for this project was done using the very excellent OpenOffice.org.